In accordance with recent enhancement in integration of chip elements such as an LSI (Large Scale Integration), a more complex circuit has been able to be mounted on a smaller chip.
In addition, development in a technique to mount elements onto the surface of a printed circuit board can mount an increased number of chip elements onto the printed circuit board.
It is sure that the above has realized the construction of a system small in size and high in performance, but on the other hand, such a system has a difficulty in testing each of the chip elements mounted on the printed circuit board.
As a solution to a test for a highly-integrated printed circuit board, JTAG (Joint Test Action Group) has proposed a method for a board connection test (i.e., a method for simplifying a connection test) confirming to the IEEE 1149.1 standard. This method for a board connection test defines the boundary scan architecture (hereinafter a JTAG circuit) serving as a connection test mechanism that is to be incorporated into a chip elements exemplified by an LSI.
Such a JTAG circuit is connected to a shifting scan chain formed by connecting input/output pins of chip elements on the printed circuit board, so that the state of the input/output pins can be controlled and observed only through scanning and shifting operations without directly probing the inputting/outputting pins.
Further, a JTAG circuit is used for a test for a printed circuit board on which a chip element on which the JTAG circuit has been mounted, which test is exemplified by a connection test between electronic elements connected to the printed circuit board via a connector and the chip element including the JTAG circuit (see below Patent References 1-4).    [Patent Reference 1] Japanese Patent Application Laid-Open No. HEI 11-174122    [Patent Reference 2] Japanese Patent Application Laid-Open No. 2003-57301    [Patent Reference 3] Japanese Patent Application Laid-Open No. HEI 10-186006    [Patent Reference 4] Japanese Patent Application Laid-Open No. HEI 11-52025
Recent development in a technique to mount elements onto the surface of a printed circuit board enables a single LSI to be connected to a large number of electronic elements via connectors. That requires one-to-many connection tests in addition to one-to-one tests disclosed in the above Patent References 1-4.
For example, for a printed circuit board 104 to be tested which includes, as depicted in FIG. 6, an LSI 101 with a JTAG circuit 100 and a number of connectors 103a-103d to which electronic elements 102a-102d (e.g., a memory element or another printed circuit board) connected to the LSI 101 through signal lines are connected, a one-to-many connection test is required for connections between the LSI 101 and the electronic elements 102a-102d. 
In performing a one-to-may connection test between the LSI 101 and the electronic elements 102a-102d, there is proposed a technique in which testing loop-back devices (hereinafter called connection test devices) 105a-105d, which returns as a response signal a signal inputted as a response signal, are connected one for each of the connectors 103a-103d to substitute for the electronic elements 102a-102d as depicted in FIG. 7.
The JTAG circuit 100 outputs a test signal to a number of connection test devices 105a-105d through signal lines a1-a4 and verifies the state of connections between then LSI 101 and the connection test devices 105a-105d from whether or not a signal identical with the output signal returns to the JTAG circuit 100 through signal lines b1-b4.
Here, the state of connections between the LSI 101 and a number of connection test devices 105a-105d represents whether or not the state of a connection between the printed circuit board and each connector is normal and/or whether or not a number of nets (i.e., signal lines a1-a4 and b1-b4 that connects the LSI 101 to the connectors 103a-103d) of connectors 103a-103d are normally connected.
However, if one of the connectors 103a-103d is abnormal (due to failure) when a connection test is performed on the LSI 101 on which the connection test devices 105a-105d are connected all the connectors 103a-103d, the LSI 101 receives a response signal identical to the output test signal and therefore does not detect the abnormality.
Similarly, if one or more of the signal lines a1-a4 and b1-b4 are abnormal due to disconnection or the like but at least one pair of signal lines a1 and b1, signal lines a2 and b2, signal lines a3 and b3, and signal lines a4 and b4 are normal, the LSI 101 receives a response signal the same as the output test signal and therefore does not detect the abnormality.
For another method for a one-to-many connection test between the LSI 101 and the electronic elements 102a-102d, a single connection test device 105a is sequentially connected to one of the connectors 103a-103d to carry out connections of the connectors 103a-103d one at a time.
However, the operator sequentially connects the connection test device 105a to each of the connectors 103a-103d to change connectors 103a-103d to be tested. That requires a large amount labor by the operator and a large time for the test.
In addition, since the operator connects the connection test device 105a to each of the connectors 103a-103d by hand, there is a possibility in occurrence of a human error such as forgetting to test one of the connectors 103a-103d but the operator believes that the all the connectors each have been connected and tested, or connecting and testing one the same connectors twice. Moreover, such an error cannot be automatically detected and therefore there is possibility that the test for all connectors 103a-103d cannot be accomplished.